Getting Started with Xilinx’s Chipscope IBERT for Gigabit Transceiver applications and Debugging High-Speed Serial Links
Today, more and more of my customers starting new designs are using some form of gigabit transceiver links. Some are using them for board-to-board data interfaces, some for camera interfaces, some for storage device interfaces and some for PC interfaces via PCIe. The list goes on and on. An oddity here is that most of these engineers have little or no high-speed serial link experience and must come up to speed as quickly as possible on this technology. This, however, is not an easy technology to master. Fortunately Xilinx has created the Chipscope IBERT tester along with highly flexible gigabit transceivers to help minimize design time and improve debugging capability.
Xilinx, now on their 5th generation of gigabit transceivers, has developed a very advanced and easy-to-use gigabit transceiver. Don’t assume this applies to only Virtex customers because now even Spartan-class FPGA’s will have gigabit transceivers with the Spartan-6 family! Gigabit serial links are becoming ubiquitous and companies are demanding more expertise in this area from their engineers. Speeds of these devices are ranging from 100Mbs all the way up to 10Gbs. At these speeds, debugging transceiver links is extremely difficult, but not with the Xilinx Chipscope IBERT. The IBERT has the ability to control, monitor, and change the gigabit transceiver parameters and perform bit error rate testing. Most importantly, this can all be done absolutely independent of the FPGA design.
As noted, no FPGA code is required to make this work. The Chipscope IBERT creates its own .bit file which you can program into your FPGA! So all you need is a PC with Chipscope Serial I/O Toolkit (EF-CSP-SIOTK-NL, $695 for Node-Locked License) or any “Edition version of IDS, Xilinx JTAG Cable (HW-USB-II-G, $225), and a PCB with the following:
- Transceiver enabled Xilinx FPGA.
- Transceivers must be powered on the FPGA/PCB
- System, or “fabric” clocks for driving FPGA Fabric
- Reference clock for driving gigabit transceivers (see transceiver datasheet for each FPGA family for required clock speeds.)
To download the Chipscope toolkit, visit:
For Virtex-4 and Virtex-5 designs, here is how you do it:
How to launch the IBERT Generator:
Programs - Xilinx ISE Design Suite - Chipscope Pro - IBERT Core Generator
Then follow the simple directions found in Chapter 2 of Chipscope Pro IBERT Core Generator User’s Guide (UG213). (see note below on clock settings)
In the setup of the IBERT core you will be able to:
- Set which gigabit transceivers are enabled
- Enable different pattern generator settings, including
PRBS 7-bit to 31-bit
- Enable GPIO for controlling external devices, such as a SFP optical module.
- Create batch mode argument files.
NOTE: The Clock settings are a bit confusing on the IBERT Core Generator. Two independent clock sources must be available to make the core work. The IBERT Core requires a System Clock, or “fabric” clock source in addition to the gigabit transceiver clock source. I like to call the System Clock source the “fabric” clock source as it is used to clock the logic that produces the pattern generator and error detector. This clock must come from a I/O pin of the FPGA.
- For Virtex-4 designs, this clock must be between the frequencies of 32MHz and 210MHz.
- For Virtex-5 designs, the clock must be between the frequencies of 10MHz and 100MHz.
The gigabit transceiver clock must be connected to a reference clock pin of the gigabit transceiver interface and frequency is typically dictated by the interface speed. For example, in Virtex-5, 3Gbs interfaces can input 300MHz, 150MHz, 100MHz, 75Mhz frequencies to name a few.
PCIe NOTE: Another note for PCIe Customers who may not have a System, or “fabric” clock, and use the recovered clock to drive the fabric and do not have two clock sources, there is a solution, This is supported in the newer versions of the tools and lauched from within Coregen:
- Available in 11.4 with IBERT for Virtex-6 and Spartan-6.
- Available for Virtex-5 GTX in 12.1 and Virtex-5 GTP in 12.2.
For Virtex-6 and Spartan-6 designs, the IBERT Wizard can only be launched via Core Generator. But follows a similar wizard to the Virtex-4/5 wizard.
Start - Programs - ISE Design Suite - ISE - Accessories - Core Generator
In Core Generator, under IP Catalog select:
Debug & Verification - Chipscope Pro - IBERT …
Once the Core has been generated, it must be programmed into the FPGA. And this can be done using Chipscope. Open the Chipscope Analyzer:
Programs - Xilinx ISE Design Suite - Chipscope Pro - Analyzer
Under the Device pull-down menu, select the FPGA and select configure. A series of instructions will guide you from there. Once configured, select Window à New Unit Windows and then the IBERT core. In here you will be able to control the following settings of the gigabit transceiver (in this example, the target is a Virtex-5 FPGA). Here are some of the useful features:
- Clock Settings Panel
- Determine PLL Status, here you can see if your PLL is locking to the input REFCLK
- Identify location of tiles, Status of Power settings, Line coupling and Clock Frequency
- MGT /BERT Settings Panel
- Determine MGT Link Status, Is your MGT locking to the input?
- Change the Loopback Mode… Did you know you can loopback the MGT outputs back into the RX channel of the MGT? You can do this in the PCS (digital section) or PMA (analog section). And vice-versa, you can loopback RX data and transmit it back out a TX port.
- Channel Reset. You can completely reset the MGT with this.
- Edit DRP… Did you know you can edit any MGT attribute by clicking on the Edit DRP button? What can you edit here? (NOTE: First thing you should do is export your current settings: Click Export Settings. That way you’ll save your starting point.)
- RX/TX Termination
- Edit the Line Rate (by changing the MGT’ Internal PLL settings)
- Enable or disable 8b/10b encoding
- Transmit Settings
- Change TX Polarity
- Inject TX Bit Errors
- Enable TX Differential Boost
- Change the TX Pre-Emphasis, useful for tweaking output to create wider, cleaner eye-diagrams. All customers should try this across their backplane to increase robustness of signal integrity.
- RX Setting
- Change RX Polarity
- Change RX Coupling and Termination Voltage
- Change/Enable the RX Equalizer, I’ve used this on several occasions to enhance customers signal integrity. For slower speed designs (<1Gbs), you should disable this feature as it mixes in high frequency content with wideband content. For higher frequency designs, you should take more high-pass content and reject more wideband content. This is a very useful setting to play with, especially if your links see intermittent errors.
- RX Sample Point. This is perhaps one of the most underused but beneficial features. The MGT automatically centers the clock to the data eye. But how wide is your data eye? With this you can slide the clock back-and-forth from the center of the data eye until you see data errors. With this you can calculate the width of your data eye! And if you loopback you serial link across your cable or backplane, you can test the quality of your physical interface. Pretty cool huh?
- BERT Settings
- Change your TX/RX Data patterns on-the-fly
- RX Bit Error Ratio, Error Counters and BERT Reset
In conclusion, I can’t tell you how many customers I’ve had call me and say they are seeing anomalies on their gigabit transceiver links but have not used Chipscope’s Serial I/O Toolkit to debug them. This tool is invaluable when it comes to identifying and resolving line issues. Further, even if your design works right out of the shoot, this tool should be used to maximize signal integrity and create robust designs. The flexibility of the Xilinx gigabit transceivers allow engineers to maximize their high-speed links without turning their PCB. That’s something that can save any company money! And these days, that’s critical…
The following documents provide further information:
UG213, Chipscope Pro Serial I/O ToolKit
UG029, ChipScope Pro Software and Cores User Guide [Ref 1]
UG076, Virtex-4 FPGA RocketIO Multi-Gigabit Transceiver User Guide [Ref 4]
UG196, Virtex-5 FPGA RocketIO GTP Transceiver User Guide [Ref 5]
UG198, Virtex-5 FPGA RocketIO GTX Transceiver User Guide [Ref 6]
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