Written by: E. Cordeiro, Avnet Field Applications Engineer
As I explained in the previous parts the motivation I had to write this blog is that when working with FPGAs people usually forget that the FPGA is based on some fixed blocks like look-up tables (LUT), flip-flops (registers), and memory blocks that are predefined and are not completely flexible.
In this part I will talk about the DSP blocks that are available in the Virtex 4, 5 and 6 and the Spartan 3A DSP and 6. As it is available now in the high performance and in the low cost families it interesting to know what are they capable to do in case you have some DSP blocks that are not being used in your project.
To start our conversation about the DSP block let’s take a look on it:
Figure 1: Spartan 6 DSP Block
This block is a Spartan 6 DSP block, but the other families DSPs blocks are similar to this one. They have bigger inputs in Virtex 6 and don’t have pre-adder in Spartan 3A DSP and Virtex 4 and 5.
Analyzing the picture you can notice that the DSP block is basically a multiplier and an adder with some pipeline registers. Using this basic observation we start thinking what can we do with unused blocks and the first ideas are:
- A multiplier
- An adder
- An accumulator
- A MACC – multiply accumulate
- A multiplexer
You might be thinking that it is possible to implement all this functions using the FPGA logic, so what is the advantage to use the idle DSP block?
The advantage is that the DSP block is a dedicated block inside the FPGA and it is optimized to run close to the maximum FPGA speed and the routing inside the FPGA is only needed to take the signals in and out of the block, there is no need to route the signals during the math function from the multiplier to the adder for example. Another advantage is that the savings you make on your logic part may enable your project to run.
If want the templates of how to implement those functions in DSP blocks take a look in the UG073 from Xilinx. In this user guide you will also find other advanced uses for the DSP Blocks.
This blog ends this first series of “Small details that make difference on a FPGA project”. If you have any suggestion of other small details that make difference send me a message.
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