10-11-2010 01:38 PM
Welcome to the Avnet 'FPGA-based System Design with High-Speed Data Converters' forum. This site is dedicated exclusively to Xilinx FPGA-based data acquisition among workshop attendees. Presently, it is not open to the general Avnet customer base.
Right now we are finalizing the last updates to the lab instructions and reference designs to provide the highest-quality design tutorials. We plan to post the material on the Avnet server this week, at which time we will notify you by e-mail and through this forum.
Stay tuned for instructions to download the workshop material from the Avnet server later this week.
Global technical Marketing, DSP
07-24-2011 07:17 PM
I attended your 'FPGA-based System Design with High-Speed Data Converters' course in Singapore during the last March. Currently, I am implementing the same interface design using IODelays & ISERDES primitives running at 500Mbit/s with a deserialization factor of 4 in Virtex 5. I have performed post-layout simulation using ModelSim 6.3e and looked into the input clock & data signals to all the ISERDES. I realized the input clock edge is not aligned to the center of the data eye. I was wondering if I should adjust the phase of the clock using the PLL such that it is aligned at the center of the data eye. Please advise. Hope to hear from you soon. Thanks.
02-15-2012 01:10 PM
Could someone be kind to share me the course material? I am going to start some similar design with FPGA based platform.