Interfacing DDR3 and LPDRAM with the Xilinx Spartan®-6 Hard Memory Controller

[Bobgf]

Hello,

What is the maximum addressing space  for external DDR2/DDR3 module if design with MIG? The address bus width is 31 in MIG. Exteranl Memory data bus is 8-Byte wide. Is it 16GB?

[bhfletcher]

Spartan-6 does not support DDR2/DDR3 modules.  The Spartan-6 MCB supports single components, as shown in Table 3-1 in UG388.

The largest component configuration supported by the MCB, according to Table 1-3 in UG388, is a 4Gx16 DDR3 device.  This implies that the MCB was built to support enough address bits to support a 4Gx16 device.   Looking at the physical I/O on the S6 FPGAs, the maximum address pins that I see from a single MCB is 15 address and 3 bank address.

The User Interface command port includes a 30-bit address, although these are the ms-bits.  Depending on the size of the data port, two to four of the ls-bits are implied.  See Table 4-2 in UG388.  The external memory is mapped to the User Interface addresses as shown in Table 4-4 of UG388.

Bryan