11-22-2011 11:37 AM
My apologies. The Avnet DRC is undergoing a major overhaul and some files have gotten lost in the transition. Attached are the XBD (PLB) and IPXACT (AXI) file sets for the Xilinx EDK Base System Builder wizard.
11-22-2011 03:10 PM
Thank you very much for the files. I have tried using these files in Xilins Platform Studio (13.2) to create a very default microblaze design(PLB) with just default configuration and peripherals running the "standalone" OS.
Running the a "Hello world" application from the internal bram works fine without any problems, however trying to run the application from the DDR3 ram i get an "elf verify error" at 44%. The same applies if i try to make a simple design with the AXI bus instead. - It is like the softcore processor cannot access the DDR3 to write/read for some reason.
Any suggestion where i might be doing something wrong?
Thank you again,
11-22-2011 03:17 PM
Just to note,
We try to run the application from the DDR3 by setting the linker script to point towards the DDR3 adresses - Same way we did with out Spartan3E-Starter board where we had no problems.
11-22-2011 04:14 PM - edited 11-22-2011 04:16 PM
The issue with running your design from DDR3 may not be a problem with your design. The errata for this board (posted on the DRC) describes a known problem with the DDR3 interface and the default bitgen settings. By default the bitgen settings for any XPS project attach pulldowns to any unused signals on the FPGA. This breaks the FPGA designs using the MCBs. To fix this, change the bitgen settings to allow unused pins to float. Add this line to the etc/bitgen.ut file of your XPS project:
-g UnusedPin: Pullnone (remove the space between the ':' and 'P')
This should fix the problem.