We have a strange error when communicating via TCP/IP.
Client (Windows) <--> Server (FPGA Board)
TCP Traffic (logged by Wireshark)
0. Idle (No communication)
1. Client commands Server to continuously send TCP messages => OK
2. Server continuously sends TCP messages (~10ms between each TCP message)=> OK
3. Client commands Server to stop the sending of TCP messages => (*) Strange behaviour almost every time we try this!
(*): During 3. TCP messages get corrupted.
Each TCP message has a user payload part that is 16240 bytes (a small user header followed by user data).
In Wireshark we see that the TCP message gets divided into several TCP packets.
But the problem is that we see a lot of zero’s in the user payload part (both the user header and user data)!
Xilinx Software: ISE 12.4
Hardware:
My own baseboard (carrierboard) that can carry one FPGA Module (Avnet/Silica)
FPGA Module (Avnet/Silica): Xilinx Virtex-5 FXT Mini-Module Plus (FX70T)
Part Number: AES-MMP-V5FXT70-G
Xilinx Tool Flow:
ISE: Started a new project and added a “EDK system”, top vhdl, my own vhdl files and ucf file.
EDK: I have used the Avnet Silica’s BSB Wizard for the FX70T FPGA Module to generate template files (.mhs and .ucf) that I have adjusted to match my own baseboard.
SDK: Created a HW platform project, BSP project (xilkernel and lwip), C++ project.
Can this be a Hw issue (board, FPGA)?
Regards Magnus
