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04-24-2013 03:28 AM
I've been recently experimenting with the USB Interface on Virtex-5 Mini Module XC5VFX70T.
Using ChipScope, I'm monitoring the interface signals (Next, Stop, DataDirection, Data) while connecting to a PC and in another case a USB Peripheral.
I'm fairly new to USB interface programming on FPGA.
- Could you please explain why I'm getting the same readings in both cases?
- Could you please point-out any reading material? (not for USB Protocol, but for XC5VFX70T application notes or white papers)
I don't require a core to implement USB stack, rather just to be able to monitor the difference when connecting to Host/Peripheral.
Any feedback is appreciated!
04-24-2013 04:28 AM
The USB example design provided for this module on our web site supports Peripheral only (we do not have a host example design). All Virtex-5 documentation can be found on Xilinx web site at http://www.xilinx.com/support/index.html/content/x
04-24-2013 04:47 AM - edited 04-24-2013 04:49 AM
Thanks for your reply.
I've previously accessed these documents and example designs. As for the example design, it includes a ready made core that acts as a peripheral as you've mentioned.
Based on ChipScope readings, the Data Direction(DIR) signal of the USB interface is high whether I connect to a host(PC) or a peripheral(USB Stick). And in both cases, Data is x"00".
- Shouldn't there be a difference between the two connections?
04-24-2013 06:02 AM
I've partially read the ISP1504A1 datasheet. According to the datasheet, the DIR signal should change between LOW and HIGH.
Whether, I connect to a host or peripheral DIR is always HIGH which basically indicates that it has data to send to the link while Data is x"00".
- Shouldn't it differ between the two connections?
PS: I didn't get your attachment.
04-24-2013 06:38 AM
When using the Avnet provided USB reference design with this module, you should see a direction change on the DIR signal depending on whether you are reading from the V5 module or writing to it. For example, if you open a file stored in the V5 module, you should see the DIR low. When writing to the V5 module (saving a file) you should see the DIR signal high.
04-24-2013 07:07 AM
Thus having similar values(Stop = 0, Next = 0, DataDirection = 1, Data = x"00") in both cases(Host, Peripheral), means that I'm required to write Data to the Host/Peripheral.
Please correct me if I'm wrong!
Furthermore, if I disconnect completely in either case I still end up with the same values!
PS: The simple test project that I've made is a VHDL module with an IP Core ICON and VIO.
04-24-2013 07:33 AM
I'm simply monitoring interface signals in case if I connect the Mini-USB on the board to a PC and in another case to a USB Stick. And the IP Cores that I'm using are only related to ChipScope i.e. I'm not using any dedicated IP Core for the interface. I'm only reading the interface signals and monitor the change if any.
This interface signal changes (if any) is an important information that will be in used as part of a bigger implementation that isn't directly related to USB IP Cores.
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