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03-17-2010 10:24 PM
according to MIG documentation and Xilinx Application notes,RST_DQS_DIV trace delay needs to be equal to sum of trace delays of DDR clock and DQS and it's been properly commented in schematic of Spartan3A-DSP.
but in net lenght report of the board layout,total trace length of RST_DQS_DIV is nearly matched to DDR clock/DQS trace and it is not sum of them at all.
e.g total DDR clock (including pre & post series termination) = 3613mils,total DQS trace length = 3813 mils so RST_DQS_DIV needs to be 7426mils approximately but it is only 3794mils.
I would appreciate if anybody can clarify this issue for me.
03-18-2010 09:48 AM
The trace length needs to be the equal to sum of trace delays of DDR clock and DQS, as documented in the schematics.
I asked one of our hardware designers to check this trace length on the Rev.C board.
Using the PADS, the tool in which the board was designed, the trace length is 6.9126”.
How did you take your measurement ?
For which hardware revision did you make your measurement ?
03-18-2010 04:46 PM
it is Rev 1 of Spartan 3A DSP starter kit(XtermeDSP).
I looked at net lenght report(which is an excel file) accompanying with Gerber files.you can find it attached.
do you think this report has error?maybe daVinic Board has different routing lenghts.
03-19-2010 09:29 AM
Sorry, I thought you were talking about the Spartan-3ADSP DaVinci co-processing board.
I asked one of our hardware designers to check this trace length on the Spartan-3ADSP Starter Kit Rev.1 board.
Using the PADS, the tool in which the board was designed, the trace length is 6.905” (plus the length of the series resistor).
Where did the "net length report" excel file come from ? (I did not see it in attachment)
Did this come from the Avnet DRC web site ? or the Xilinx web site ?
I will try to find out why it does not have the same information.
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