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I2C issues in hardware and software
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11-19-2009 08:32 PM
Hello everyone,
I'd like to share some experiences of using IIC with this Spartan 3A Evaluation Kit.
The provided example "Avt3S400A_Eval_MB_I2C_temp_v10_1_00 MicroBlaze IIC Temperature Sensor" works. However, when connecting other I2C devices to the onboard I2C connector, it did not work for me initially. I think the problem is that when using FPGA as I2C master as in the above example (the PSoc chip can also act as I2C master, but I don't use the onboard PSoc), the board lacks open collector drivers for SDA and SCL, in other words, it does not meet I2C standard. Here is what's stated in the XPS IIC core document:
"The XPS IIC does not provide explicit electrical connectivity to the IIC bus. The module expects the
design to include bi-directional I/O buffers which implement open collector drivers for the SDA and
SCL signals. Consequently, the user must provide external pull up devices to properly hold the bus at
the logic 1 state when the connection to ground is removed."
After adding off-board open collector drivers, my interface to other I2C devices worked.
The example software looks like to be modified from Xilinx examples for the I2C driver. To me, there seems to be full of confusions. The following are examples.
I guess ordinary persons would interpret "while (TransmitComplete) { }" as "wait while transmit is complete". The original Xilinx programmer wrote it to act as ""wait while transmit is NOT complete". It looks like they lack basic peer code review so that such bizarre code get to reach customers.
More confusing part is that in WriteData(...) and ReadData(...), XIic_MasterSend(...) and XIic_MasterRecv(...) are called twice respectively. I initially thought the dual call is needed because of repeated start. But later I found the 2nd call is not necessary. If you print out 1st 5 or so elements in the receive buffer after first XIic_MasterRecv(...), you'll find that 2 bytes are already received after the 1st XIic_MasterRecv(...).
I'm also not sure if the following line is needed since variable BusBusy is not referenced again in later code.
/*
* This is for verification that Bus is not released and still Busy.
*/
BusBusy = XIic_IsIicBusy(&IicInstance);
For me, the quality of example driver code for IIC core casts doubt on the quality of IIC IP core: 1) it might not be well tested. 2) the person who wrote the IIC core might be the same person whol wrote the driver code.
How is your experience with I2C on this board if you used it before?
regards,
bobf
Re: I2C issues in hardware and software
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11-20-2009 07:43 AM
bobf,
I think Xilinx would welcome your questions and critique. Since this forum is limited to owners of this particular board, you may find you get a broader response by also posting on the Xilinx forums (http://forums.xilinx.com/xlnx/), opening a case with Xilinx support (http://www.xilinx.com/support/clearexpress/websupp
Bryan
Re: I2C issues in hardware and software
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11-20-2009 10:29 AM
Hi Bryan,
Thanks for your suggestion.
For Avnet, I'd like to suggest that for future similar evaluation board design, it'd be nice to consider if I2C specific hardware drivers are needed in order to meet I2C standard.
Thanks,
bobf
Re: I2C issues in hardware and software
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08-12-2010 05:52 AM
Hi bobf,
Could you please send me this sample project? I couldn't find it at Avnet nor Xilinx website. I searched the EDK directory for it... but.. nothing was found.
So... you have just mapped the I2C to the external GPIO? What about the external driver? Only the external pull-ups were really needed?
Thank you.
Rick



