04-21-2009 11:56 PM
What can you tell me about this item: "AES-MXP-SRAM-G
MXP SRAM MODULE - FOR USE WITH SPARTAN 3A EVAL".
The product site is pretty dense about navigation or showing product information.
The 3s400 eval board would be a great little platform for experimentation if not for the lack of RAM and sparse I/O. For example, adding even a VGA and its buffer is nigh impossible. I understand there is only limited I/O with the small device.
What can you tell me about the SRAM device? Does it use up the few I/O pins on the board? I got curious when I saw the SRAM option in the EDK XDB device list.
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04-22-2009 10:32 AM - edited 04-22-2009 10:33 AM
You can always find additional information in our Design Resource Center (DRC) about Avnet supported boards and kits. The DRC is located under the "Design" tab.
Here is a direct link to the evaluation kit you are referring to:
If you click on the "Support Files and Downloads" button you will find the user guide, technical documentation, and software.
04-22-2009 09:14 PM
Thanks for the info. I found the "Design Center" tab on the search results page after a few moments. That took me to the info page you posted.
Please let me know if there's a more appropriate place to ask this. The 1Mx8 SRAM is somewhat small, and eats up quite a few of the very limited I/O pins. How difficult would it be to implement an SDRAM solution? If I stay away from the DDR parts, will I still have to worry about matching trace lengths, etc? How much setup is involved in modifying the XBD to support the memory? In general, where in the mountain of Xilinx docs should I start reading? But first, I guess the important question is whether this is a reasonable solution for the 3S400A eval board. I have in mind the Micron MT48LC8M8A2TG-75:G TR (SDRAM, 8Mx8) or similar. My interest is the larger storage and the smaller address bus.
04-23-2009 12:54 PM
I agree that your choice of SDRAM is a better memory density for pins used. SDRAM is (IMHO) easier to connect to an FPGA than SRAM - I have a preference for synchronous interfaces.
Regarding trace length matching - that really depends on the speed you will be running. Keep it well under 100MHz and you won't have an issue. 64MHz comes to mind - that's a 4x of the input clock.