Spartan 3A Evaluation Kit

[benoit]

Hello,

I have a problem with the "Avt3S400A_Eval_Microblaze_V10_1_03" tutorial.

First, I generate the netlist. EDK find no errors but displayed 12 warnings : 

WARNING:MDT - PORT:IWAIT CONNECTOR:ilmb_LMB_Wait -

   C:\Xilinx\10.1\EDK\hw\XilinxProcessorIPLib\pcores\microblaze_v7_10_a\data\mic

   roblaze_v2_1_0.mpd line 196 - No driver found. Port will be driven to GND!

...

WARNING:MDT - PORTeripheral_Reset CONNECTOR:sys_periph_reset -

   C:\tmp\FPGA\Tuto\MicroBlaze\system.mhs line 231 - floating connection!

Then, I generate the bitstream. There is still no error found but 144 warnings are displayed :

WARNING:Route:455 - CLK Net:sys_clk_pin_IBUFG may have excessive skew because 

      1 CLK pins and 0 NON_CLK pins failed to route using a CLK template.

...

WARNINGhysDesignRules:812 - Dangling pin <DOB31> on

   block:<microblaze_0/microblaze_0/Area.Using_ICache.ICache_I1/Data_Memory/Usin

   g_B16_S36.Using_S36_Spartan3A.RAMB16BWE_I1>:<RAMB16BWE_RAMB16BWE>.

Then, I compile the Peripheral project . There is still no erro found but 1 warning is displayed :

WARNING: Software Settings for CORE_CLOCK_FREQ_HZ 100000000 is not same as the

Processor frequency defined in Hardware (MHS) 66666667. Please ensure that

Software Settings has the right value as specified in Hardware.

Then,  I merge bitsream and software test application in one download.bit file. This file is loaded into the board. The following is what is displayed on the receice console of AvProg tool :

FPGA programmed successfully! 

þþþðþþþðððþþÀþðþþÀþþþþðþððþþðþþðþþþðþðððþþþðþðþþþððþðþððþþððþþþþþðþððþþþþþþþþðþðþðððþþþðþþþðþþðþþþðþððþþþþþþðþþðþþþðþþðþþþðþððþÀþþþþðþþþþþþðþþþþþÀþþþþþþþþÀþþþþÀþþþþþþþþþþÀþþþþðþþðþðþðððððþþþþððþððÀðþþþÀþÀÀþþðþþþþþÀþððþþððþÀþþþðþððþððþðþþðþþÀþþþþðþþþþþþðþþþþþÀþþþþþþþþÀþþþþÀþþþþþþþþþþÀþþþþðþððþþþþþþþðþþþðþþþþÀþÀÀþðþðþþðþþþðþððþþþþþþðþþðþþþðþþðþþþðþððþÀþþþþðþþþþþþððþðþþþþþþþþÀþþþþÀþþþþþþþþþþÀþþþþðþþðþðþðððððþþþþððþððþþþðþþþþþþþþþþþþþþðþþðþþþþþðððþþððþÀþþþðþððþððþðþþðþþÀþþþþðþþþþþþððþðþþþþþþþþÀþþþþÀþþþþþþþþþþÀþþþþðþððþþþþþþþðþþþðþþþþÀþÀÀþðþðððððþþþþðþþþÀðþððÀðþþþÀþþþþðþðþðþþðþþðþþþðþððððþþþþþþðþþðþþðþþþðþþðþþþðþððþððþþðþþþÀþþðþþþþðþÀþþððþÀþþþþþðþþðþÀþþþþÀþþþþþþþþþþÀþþþþðþþðþðþðððððþþþþððþððÀþþþþþÀþþþðþþþþþþþþðþþþþÀþððþþðþþþðþððþþðþððþððþðþþðþþððþþðþþþÀþþðþþþþðþÀþþððþÀþþþþþðþþðþÀþþþþÀþþþþþþþþþþÀþþþþðþððþþþþþþþðþþþðþþþþÀþÀÀþþþðþþþðþððþþþþþþðþþðþþþðþþðþþþðþððþþþþþþþððþÀþþÀðþþðþþÀþþþþðþþðþþþþðþÀþþððþÀþþþþþðþþðþÀþþþþÀþþþþþþþþþþÀþþþþðþþðþðþðððððþþþþððþððÀðþþþðþðÀþþþþþþðþþþþþþþþþþþÀðþþþþþÀþþþþðþðþððþððþðþþðþþþþþþþþððþÀþþÀðþþðþþÀþþþþðþþðþþþþðþÀþþððþÀþþþþþðþþðþÀþþþþÀþþþþþþþþþþÀþþþþðþððþþþþþþþðþþþðþþþþÀþÀÀþþþðþþþþðþþþðððþþÀþþþðþþÀþþþðþþðþþþðþððþþþþþþþðþþðþþþðþðþðððþþþðþþþðþþðþ

As I am new in FPGA, I don't know on which part of the project I could search a mistake.

Think you for your help.

[bhfletcher · Accepted solution]

The warnings can be ignored.  If you are frustrated with the number of warnings, please provide that feedback to Xilinx as they are inherent in any MicroBlaze design.  Xilinx feedback can be given at www.support.xilinx.com.

This looks like a baud rate issue to me.  Do the Comm settings in AvProg match the setting you selecting for the MicroBlaze UART in Base System Builder?  Note that the current PSoC firmware has a lower baud limit on the USB-UART bridge of 19200.   Step 12 in the tutorial instructs you to set the MB's UART to 115200, which you can verify in the MHS file:

BEGIN xps_uartlite
 PARAMETER INSTANCE = USB_UART
 PARAMETER HW_VER = 1.00.a
 PARAMETER C_BAUDRATE = 115200
 PARAMETER C_DATA_BITS = 8
 PARAMETER C_ODD_PARITY = 0
 PARAMETER C_USE_PARITY = 0
 PARAMETER C_SPLB_CLK_FREQ_HZ = 66666667
 PARAMETER C_BASEADDR = 0x84000000
 PARAMETER C_HIGHADDR = 0x8400ffff
 BUS_INTERFACE SPLB = mb_plb
 PORT RX = fpga_0_USB_UART_RX
 PORT TX = fpga_0_USB_UART_TX
END

The default baud rate for AvProg is 115200, but you can change it as well.

Bryan

[benoit]

That's it : the FPGA uart is configured with a baudrate of 9600 bauds while the PSOC uart baudrate is set to 115200. I have changed the FPGA baudrate to 115200 bauds an now it works well.

Think you.