07-17-2012 10:16 PM
Im new to FPGA design. I have implemented ethernetlite and lwip (lwip_echo_server) on the IVK board using the Base_Platform_Demo project, and it worked well. I used the same ethernelite configuration as the sample code from LX150T development kit.
But when I tried to use it in the IVK_DVI_Processing_Demo with the same ethernet configuration (.ucf, .mhs) it did not work at all. I can not ping my board's ip. I'm assuming the problem maybe in the clock frequency. Can anyone here help me to configure ethernetlite on this IVK_DVI_Processing_demo project?. Thanks.
07-18-2012 08:41 PM
Which version of the Xilinx tools are you using ?
Can you share the MHS/UCF files for both of your designs ?
If not, did you perform a compare between the two ?
... the only differences should relate to the DVI input/output portion of the design.
07-19-2012 06:19 AM
The difference between the MHS/UCF files for both projects seems to relate only to the DVI design.
The clock frequency you may have been referring to is:
- C_CLKOUT3_FREQ for mpmc_clk0 was changed from 125000000 to 100000000
Since mpmc_clk0 is not used in the design, I don't think this is your issue.
Have you tried to run your lwip application (without DVI code) on the Ethernetlite+DVI project ?
Maybe there's something broken in the code ?
The lwip application will be using the interrupt (which is connected to timer, uart, and ethernetlite in both designs),
so make sure that no other code is trying to do something with the interrupt.
08-02-2012 11:22 PM
I finally found the problem with the code, but I dont know how to fix it. If I comment off the following commands, I can ping my board.
"Net fmc_dvidp_dvii_clk_pin CLOCK_DEDICATED_ROUTE = FALSE;
Net fmc_dvidp_dvii_clk_pin LOC = W14" (.ucf file)
But If those two commands are added, I can not ping my board.
Do you know how to fix this?. Thanks
08-06-2012 06:33 AM
I don't know how these two UCF lines could be causing an issue with the ethernet interface.
Can you perform a comparison between the design (with and without the two lines you specified) ?
Specifically, can you compare:
- contents of PAD report
The FMC-DVI's DVI input clock is known to be on a non dedicated clock input pin when placed on FMC slot #2 of the S6-LX150T board. When placed on FMC slot #1, however, this input clock connects to a dedicated input clock pin.
Is your application OK with swapping the location of FMC-DVI to FMC slot #1 ?
If yes, let me know, I will attach the UCF file from the scaler project, in which the FMC modules were swapped
in order to connect the DVI's input pin to a dedicated clock input pin.
08-07-2012 06:45 AM
Here is the UCF from the S6-IVK Scaler/OSD reference design #3.
Please use the LOCs in this file, as they are known to work.
08-13-2012 02:42 AM
Is there any thing else that I have to modify in the DVI_Processing_Demo so that It can work with fmc in slot #1?.
1. I have modified fmc_dvidp_* LOC in the .ucf.
2. I have modified the source code in ivk_top (uses FMC_ID_SLOT1 instead of FMC_ID_SLOT2).
3. I removed the "NET fmc_dvidp_dvii_clk_pin CLOCK_DEDICATED_ROUTE = false;"
I use the existing Video Clock configuration:
"NET vid_in_clk TNM_NET = vid_clk;
TIMESPEC TS_vid_clk = PERIOD vid_clk 13.5ns;
NET plb_clk TNM_NET = sys_clk;
TIMESPEC TSPLB_VID = FROM sys_clk TO vid_clk TIG;
TIMESPEC TSVID_PLB = FROM vid_clk TO sys_clk TIG;"
With this configuration the ethernet works fine but it can not detect the DVI input (fmc_dvidp_detect_tfp403(..)).