10-03-2011 08:45 AM
From the schematics it appears that only 14 address lines from EMIFA bus are going to the FPGA. My question is how do I directly access the 64MB of LP DDR connected to the FPGA from OMAP.
10-03-2011 08:56 AM
The FPGA's LPDDR is typically accessed via the Xilinx MPMC (multi-port memory controller).
This IP is available with the Xilinx EDK (embedded development) tools.
The MPMC would typically be used by an embedded processor (MicroBlaze), and well as other data paths such as video.
You could create logic that creates transactions to the one of the MPMC's ports.
10-03-2011 10:56 AM
Sorry I didn't make my question clear.
In my application I want to download a huge chunk of data to FPGA DDR from OMAP. Since only 15 address lines of EMIFA is connected to FPGA, OMAP can address only 64KB memory. I need to download 8MB data in FPGA DDR. How do I do that.
10-03-2011 11:00 AM
You can implement a base address register which implements the upper address bit that you need.
You could sacrifice part of the available EMIFA address space for this, or implement it on another interface (such as the I2C interface).
Let me know if this helps.
10-03-2011 11:12 AM
The solution suggested will really slow down my application. The overhead in transferring data defeats the purpose of using a FPGA accelerator.
While designing the board Avnet could have given an access to the entire EMIFA bus (24 address lines) in the FPGA.
Any other solution/suggestion?