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Course: High Performanc e Clocking with the Xilinx 7 series
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02-28-2012 08:47 AM - edited 04-12-2012 03:30 PM
In our continuing highlight of the Fundamental’s Track, today we will be taking a look at “High Performance Clocking with the Xilinx 7 series.”
One of the central technologies being introduced at X-Fest 2012 is the Xilinx 7 series FPGAs which introduces a unified logic architecture with a variety of on-chip, high performance clocking resources. This course will provide a comprehensive introduction to 7 series clocking by covering topics which include but are not limited to Mixed-Mode Clock Managers, PLLs, BUFx clock buffer variants, and new Multi-Region BUFMR. On a more broad level, designers will learn about several external clocking solutions. Have questions about any of those things? Don’t hesitate to leave a comment and we’ll be happy to provide you with an answer!
This course not only teaches about the ins-and-outs of our clocking resources, but students will also learn about why they are necessary, and how they support high performance sampling systems. This course is highly recommended for those looking to gain a greater understanding of the clocking capabilities of the Xilinx 7 Series because students are assured to walk away with practical and applicable knowledge. Tick tock, time is running out! Find out more information about X-Fest 2012 and register today at http://avnet.me/xfesttf!
Useful Links:
http://twitter.com/#!/AvnetDesignWire
http://www.facebook.com/xfest2012
http://www.linkedin.com/groups/Avnet-Xfest-1964327



