Virtex-6 DSP Development Kit

[hobbss]

This post will be similar to those

here:

http://community.em.avnet.com/t5/Virtex-6-DSP-Development-Kit/Signal-quality-in-the-reference-design...

and here:

http://community.em.avnet.com/t5/Virtex-6-DSP-Development-Kit/DDC-DUC-reference-design-13-1-is-not-r...

Avnet employees gave different responses to the same question, and I am not sure which is correct.

I am trying to get the base DSP reference design running on my ML605/FMC150.  While the latest version of the reference design I could find on Avnet's website was for ISE13.1, I am using ISE 13.3 (because that is what was shipped with my dev kit).  I had to modify the build options to get Chipscope to successfully download the configuration file (-g next_config_addr:NONE).  I have made no other changes to the design.

When I look at the ChipScope probes, I see very noisy signals (see attached).  I have verified that my cables are securely connected.

I am not sure where to go from here -- start changing IDELAY vals (as recommended in the second link), or following the advice in the first link.  I have a rudimentary knowledge of ISE and Verilog/VHDL, but am not an expert.  Any advice getting these signals cleaned up would be appreciated.

Edit: Follow up questions: What/Where are the "Tutorial Labs" referenced in the second link above?  I have looked through the documentation folders of the reference design and can't find them anywhere.   Am I just blind, or are they available somewhere online?  Thanks...

[hobbss]

I have managed to answer my own follow up question.  The tutorial labs mentioned are referring to the guide for the RTL Reference Design (I was originally testing the DSP Reference Design).

In any case, I got a similar result when using the RTL Reference Design (which I downloaded from the Avnet website about a week ago).  The signals were very noisy, and not recognizable as sine waves.

I tried again w/ the December 2011 code provided in the thread linked above with interesting results.  Executed as instructed in the manual, my Unit1: DDC OUTPUTnever triggered in Chipscope.  I changed the "==" condition to "<>" and increased the depth to max (1024).  At this point, the device triggered,

and I got a nice, if somewhat digitized, sine wave (see attached).  However, the frequency is lower than I expected, and I am not sure why the trigger functionality needed to be changed.  Am I missing something simple here?

[hobbss]

Sorry for the multiple posts -- have not figured out how to attach multiple files to a single post.

When I set the fourth bit of SW1 (bypassing the DDC?), I get this result (attached) -- a very clean sine wave (obviously at an increased frequency).  Is the plot in the manual just inaccurate?