Virtex-6 DSP Development Kit

[Stephan_H]

Dear Sir or Madam,

I am trying to change the CDCE72010 register settings on the FMC150 in the reference design for the Virtex 6 DSP Kit from the "cdce72010_init_int_491_52MHz.coe"-file to the "cdce72010_init_int_737_28MHz.coe"-file.

Before the change of the register settings I generated 10 MHz sine wave in the DAC. After changing the register settings I recognized that the frequency of the sine changed to 6,66 MHz. So an increase of the CDCE72010 clock with a factor 3/2 leads to a decrease of the sine wave's frequency generated in the DAC with a factor 2/3.

I am not able to explain this but I have to solve this problem in order to advance in my work.

Thank you very much for your help!

[dsp_support · Accepted solution]

Stephan,

The FMC150 is delivered with 491.52 MHz VCXO, for use with .COE file 'cdce72010_init_int_491_52MHz.coe'. If you modify the SPI registers, then the CDCE72010 PLL may not lock. It certanily will not lock with settings in file cdce72010_init_int_737_28MHz.coe -- except possibly to some (sub) harmonic of the VCXO, with unpredictable results. Verify this on the LED_4 (where LED_0 is the 1st).

If you wish to modify the sample clock frequency to other than a sub-multiple of 491.52 MHz (by using the CDCE72010 output divider settings), then you may use an external low-jitter clock generator and bypass the PLL.

The equation relating CDCE72010 PLL output frequency to VCXO frequency is given below. Relevant settings are contained in CDCE72010 register 10. (Note M & N settings are 1 less than actual value, as explained in CECD72010 datasheet).

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)
--------------------------------------------------------------
05FC270A, <- register 10
0 5   F    C    2     7      0        A,
0101 1111 1100 0010 0111 0000 1010
M13 ... M0 = 00001001110000 => M = 625
N13 ... N0 = 00000101111111 => N = 384

0000040B,
4  0
0100 0000
FB_count = 0000010 => P = 8

Frequency (VCXO_IN or AUX_IN) / Frequency (PRI_REF or SEC_REF) = (P*N)/(R*M)

491.52/100 = 8*384/625

-------------

In recent changes to the the RTL reference design, we have increased the sampling rates of ADS62P49 to 245.76 MSPS and DAC3283 to 491.52 MSPS (with 2X interpolation in DAC3283).

regards,

Luc Langlois

Technical Marketing Director, DSP
Avnet EM

[Stephan_H]

You were right, the CDCE does not lock with the new register settings. This solved my problem. Thank you. But could you please tell me why the PLL in the CDCE does not lock with the "cdce72010_init_int_737_28MHz.coe" settings?

[mojeebshirdel]

Mr longlois : In recent changes to the the RTL reference design, we have increased the sampling rates of ADS62P49 to 245.76 MSPS and DAC3283 to 491.52 MSPS (with 2X interpolation in DAC3283).

 I've downloaded 13.1 reference design but still they're working at 61.44 and 245.76 MSPS. am I right?

[gabrielcosta]

Dear,

I have recently purchased a Avnet Virtex 6 DSP kit design. You mentioned some modifications on the .coe files of the reference design which will allow the ADC to work at 245.76 MSPS. Is it possible to have access to those files? I could not find them on the Avnet website.

Best regards,

Gabriel

[dsp_support]

Gabriel,

Here is an update of the V6 DSP Kit RTL reference design (DUC/DDC), in 13.1 tools with data converters sampling @ 245.76 MHz. Note that DAC3283 is configured for 2X interpolation, for a final output sampling rate of 491.52 MSPS at the output of the DAC. An auto-calibration block adjusts iDelays for incoming ADC data at reset-time based on a test pattern from the ADC, resulting in robust, error-free data capture.

File name: virtex6dsp_rtl_reference_design_tutorial_13_1_Dec31_2011.zip
Website link: https://avnet.egnyte.com/h-s/20111231/45da7d64d94f4230

For measuring spectral purity, I suggest the DUC/DDC be bypassed by setting the 4th DIP switch from the corner (within a bank of 8, labeled ‘GPIO DIP SW’) to ‘ON’, all other DIP switches ‘OFF’ on ML605, as shown in the release notes.

A ChipScope screen capture is attached to this post, and also in the release notes (.PPTX) within the archive, starting at the root folder à RTL\Documentation.

As you mention below, the issue with Chipscope finding no cores on the JTAG chain even after programming may be resolved with the bitgen option -g next_config_addr set to "None" instead of "0x00000". This applies to ISE releases beyond 13.1.

Please note this is a pre-release update to V6 DSP Kit. It will be ported to 13.4 and posted to the DRC with updated documentation in February.

I encourage you to validate this design on the ML605 and report the results here.

regards,

_____________________________________
Luc Langlois
Technical Marketing Director, DSP
Avnet EM

[gabrielcosta]

Hello Dear Luc,

thank you for your reply. The link seems to be broken.. can you verify it please. 

regards.

[dsp_support]

The link to the updated V6 DSP Kit reference design mentionned above has been renewed:

File name: virtex6dsp_rtl_reference_design_tutorial_13_1_Dec31_2011.zip
Website link: https://avnet.egnyte.com/h-s/20120214/745d5eb81ccf4278

_____________________________________
Luc Langlois
Technical Marketing Director, DSP
Avnet EM

[gabrielcosta]

Dear Luc, 

Thank you for posting the link once again. I have ran the ref design and it worked fine.. 

however I want to include my own design into the code instead of the DUC/DDC design. I am having trouble to analyse the signal adc_dout_i/q[15:0] using the ILA.. 

I am using a simple counter to feed the dac_din_i/q signal[15:0] and observe the received samples at the output of the ADC.. I first created a second instance of the ila_dac to be used by the adc.. just as follows..

ila_adc_inst : ila_dac
port map (
 clk => clk_245_76MHz,
 trig0 => ila_adc_trig0,
 control => ila_adc_control
);

ila_adc_trig0 <= adc_dout_q & adc_dout_i;

that did not work.. it never triggered.. on chipscope it says it is waiting for trigger.. 

in my second attempt I instantiated the ila_baseband_out just as follows..  

ila_baseband_out_inst : ila_baseband_out
port map (
clk => clk_245_76MHz,
trig0 => ila_baseband_out_trig0,
trig1 => ila_baseband_out_trig1,
control => ila_baseband_out_control
);

baseband_out_valid_sig <= '1';
baseband_out_valid_sig_v(0) <= baseband_out_valid_sig;

RX_mux_to_ILA: process (clk_245_76MHz)
begin
if rising_edge(clk_245_76MHz) then
ila_baseband_out_trig1 <= baseband_out_valid_sig_v;
if baseband_out_valid_sig = '1' then
ila_baseband_out_trig0 <= baseband_out_q_sig & baseband_out_i_sig;
end if;
end if;
end process RX_mux_to_ILA;

in this second case I assigned

baseband_out_q_sig <= adc_dout_q;

baseband_out_i_sig <= adc_dout_i;

that did not work either.. it never triggers.. 

I ve been working on it for the past 2 days with no success.. that may even be a simple thing which i did wrong but now i cant see it... in case u can have a quick look at the code I can send it.. 

thanks in advance,

gabriel

[gabrielcosta]

I found a solution. cheers