12-01-2011 09:49 PM
I have recently got ML605 with FMC150 card, I have run the reference design of DUC/DDC of xilinx 13.1
The xilinx version comes with the kit is 13.2, so i m running reference design of 13.1 to 13.2 version.
After downloading bit file and running the Chipscope the IQ output of DDC is not correct as show below!
Solved! Go to Solution.
12-02-2011 02:31 PM
The reference designs for the Virtex-6 DSP2 Kit have not been ported to IDS 13.2.
I have just verified that the 13.1 reference design "virtex6dsp_rtl_reference_design_tutorial_13_1.zip
- Tutorial Lab 1 – Verifying the RTL DUC/DDC to Golden MATLAB Vectors; Step 12 will not provide the correct "CEO Vector Window" results in the FIR Compiler Core Generator.
Your issue seems to be related to PVT (Process, Voltage, Temperature) variants among ML605/FMC150 boards. We have seen this in the past. It is possible that after time or at power-up, due to these variants, you would not see the DDC Output results as presented in reference design "virtex6dsp_rtl_reference_design_tutorial_13_1.zip
Try adjusting the iDelay values, for CLK, CH A & CH B, via the VIO Console as discussed in Steps 12 & 13 of the same Tutorial to see if that will provide the correct results.
12-07-2011 12:08 AM
After strugling with IDelay, i cant find anychange in the waveforms
1.Can you give some reference what this iDelay does to the waveforms?
2.When i open the UCF file on xilinx 13.2,there is some error with CLK_AB_P,I attached!
Kindly give me a solution asap , i have to sign the product inspection here.......
12-07-2011 11:41 AM
- you are using the original bitfile “ml605_fmc150.bit” supplied with the RTL Reference Design “virtex6dsp_rtl_reference_design_tutorial_13_1.zip
- you have installed this Reference Design according to the instructions supplied in document “RTL-AES-V6DSP2-LX240T-G-13_1-v3.pdf”, which states:
- Unzip to your computer’s C: drive using the “Extract to Here” option. The top-level folder name should be “virtex6dsp_rtl_reference_design_tutorial”. If this is not how it was extracted, then change the name as the design contains absolute path names that require this file structure.
Then you should check MMCX cable connections, ensuring they are not loose and are made correctly in accordance with Getting Started Reference Design ”virtex6dsp_getting_started_reference_design_13_1.
What LEDs are lit?
Are they “LED 5,6,7 are on indicating lock on respectively the PLL on the FMC150 and two MMCMs in the FGPA” as discussed in Step 7 of Tutorial Lab 2 – Verifying the RTL DUC / DDC in Hardware with the Data Converters Using ChipScope?
What revision of FMC150 and ML605 boards are you using?
The Virtex-6 FPGA SelectIO Resources User Guide (UG361) discusses the IDELAYCTL primitive.
The IDELAYCTRL module continuously calibrates the individual delay elements (IODELAYE1) in its region, to reduce the effects of process, voltage, and temperature variations. The IDELAYCTRL module calibrates IODELAYE1 using the user supplied REFCLK.
also found here:
Xilinx’s XAPP707 discusses in detail ChipSync technology and the IDELAY Block.
Please get back to me with the above information. If you continue to see a failure, we can discuss how to set the dip switches such that the internal DDS is driving the DAC, with DUC bypassed, which should produce a clean sin/cos waveforms at the ILA behind the DAC. This will eliminate the FMC150, except for it driving the system clock from the ADC.
12-08-2011 12:46 AM
1.LEDS 5,6,7 are on.
2.FMC150 rev 1.2 , ML605 rev D
What i does here in VIO controls is
changed the DDC/DUC Freq Enable =1:
press the centr SW9, Bus plot of DAC input shoes pure sin/cos.
but the DDC out put is still abnormal....
then i changed
DDC/DUC Frequency = 080_000 and clk iDelay = 20 to 30:
press the centr SW9, Bus plot of DAC and DDC shows pure sin/cos only in this case!!!!!!
can u send me the tested design of version 13.2....