02-14-2011 04:54 AM
the reference design generates a bitsteam without errors on 12.4 but the wavefrom at the output of the DDC (viewed using ChipScope) shows significant distortions. This is not the case with 12.3.
Any chance of getting the design updated to work with 12.4? Thanks.
11-21-2011 07:32 AM
I'm having the same issue with my design.
Both at the DDC Output and the DAC Input, the signal is totally distorted, even though I can still distinguish a sinusoid on the DAC input.
I'll post a figure later today I hope.
Also, something that I don't get is the ethernet cable.
When I configure the Virtex6 Device1 with either bitstream (the reference design also brings a bitstream of its own), LEDs 5, 6 and 7 lock as they should and lights on the ethernet go blank.
Does Chipscope even allow Ethernet connections? What's the point of the ethernet cable in this situation? And if its importat, why does configuring the FPGA shuts down the ethernet?
11-22-2011 05:22 AM
Here are the images as promised.
And DDC Output.
I think it might be a frequency issue. I've been trying to lower it through the VIO Console but nothing seems to work.
12-02-2011 02:12 AM
Sort of I guess.
Assuming the all '0' DIP Switch, I went to the "VIO Console" (on ILA0 or MyVIO depending what you get) and changed a couple of values.
"Set DDC/DUC Freq Enable" = 1
"Set DDC/DUC Freq" = '0...0'
Press the Center Button on the ML605 and you should get a good sinusoid on the DAC Input, although it's still a crappy signal on the DDC Output.
You can increase the DDC/DUC Freq, don't forget that by default the values are in Hexadecimal, but the more you increase the worse it gets.
Even so I'm not entirely sure what this DDC/DUC Freq is representing on the system. The default values they have on VHDL are 216Mhz and 52,4Mhz.