Virtex-6 DSP Development Kit

[Betotri]

Hello

I recently started working with the ML605 and the DSP Development kit. In order to get used to it I tried running the Getting Started Reference Design. Nevertheless at the beginning I had some issues with the Chipscope finding no cores on the JTAG Chain even after programming. After some research I found out the ISE 13.2 needs the -g next_config_addr to be in "None" instead of "0x00000" which is the option originally chosen in the reference project. This corrected the problem and I was able to fin the cores in Chipscope.
Anyways I go the code running on the FPGA, and kept on following the guide's instructions. The problem is that I expected that at a 61.44 MSps sampling rate of a 384kHz signal would give a clear view of the Sinusoid with good enough resolution but I am getting the following plot in the Bus Plot. (Attached File)

This plot definitely does not resemble the guide's plot. Any ideas of why Im having this problem?

Thanks in advance

[dsp_support]

Here is an update of the V6 DSP Kit RTL reference design (DUC/DDC), in 13.1 tools with data converters sampling @ 245.76 MHz. Note that DAC3283 is configured for 2X interpolation, for a final output sampling rate of 491.52 MSPS at the output of the DAC. An auto-calibration block adjusts iDelays for incoming ADC data at reset-time based on a test pattern from the ADC, resulting in robust, error-free data capture.

File name: virtex6dsp_rtl_reference_design_tutorial_13_1_Dec31_2011.zip
Website link: https://avnet.egnyte.com/h-s/20111231/45da7d64d94f4230

For measuring spectral purity, I suggest the DUC/DDC be bypassed by setting the 4th DIP switch from the corner (within a bank of 8, labeled ‘GPIO DIP SW’) to ‘ON’, all other DIP switches ‘OFF’ on ML605, as shown in the release notes.

A ChipScope screen capture is attached to this post, and also in the release notes (.PPTX) within the archive, starting at the root folder à RTL\Documentation.

As you mention below, the issue with Chipscope finding no cores on the JTAG chain even after programming may be resolved with the bitgen option -g next_config_addr set to "None" instead of "0x00000". This applies to ISE releases beyond 13.1.

Please note this is a pre-release update to V6 DSP Kit. It will be ported to 13.4 and posted to the DRC with updated documentation in February.

I encourage you to validate this design on the ML605 and report the results here.

regards,

_____________________________________
Luc Langlois
Technical Marketing Director, DSP
Avnet EM

[dsp_support]

The link to the updated V6 DSP Kit reference design mentionned above has been renewed:

File name: virtex6dsp_rtl_reference_design_tutorial_13_1_Dec31_2011.zip
Website link: https://avnet.egnyte.com/h-s/20120214/745d5eb81ccf4278

_____________________________________
Luc Langlois
Technical Marketing Director, DSP
Avnet EM

[gabrielcosta]

Hello Luc,

I have been working on the update version of this referece design and so far it is working very well.

I would like to ask you something. The DAC output has an output of 1 Vpp. The ADC are configured so that they have an internal 6dB gain which reduces its full scale input range from 2 Vpp to 1 Vpp. If we use the loop back configuration with the reference design should not the digitized samples at the ADC range from -32768 to 32767? That is not what happens. The maximum value of the digitized samples is something around 25000 which gives a 1.3 reduction factor. Do you know the reason for this?

Regards.

[John_E]

I had the same experience as Betotri. The new version of the code solved the problem.

[gabrielcosta]

I have been working on the update version of this referece design and so far it is working very well.

I would like to ask you something. The DAC output has an output of 1 Vpp. The ADC are configured so that they have an internal 6dB gain which reduces its full scale input range from 2 Vpp to 1 Vpp. If we use the loop back configuration with the reference design should not the digitized samples at the ADC range from -32768 to 32767? That is not what happens. The maximum value of the digitized samples is something around 25000 which gives a 1.3 reduction factor. Do you know the reason for this?

Does anyone have an answer to that? 

regards

[gabrielcosta]

Ok, 

I believe this is due to the low pass filter at the output of the DAC.. there is minimum frequency limitation of 3MHz.. I was using a sinusoid at 4MHz. That maybe the reason.. 

regards 

[rdisanto]

Hi Gabriel,

I have encountered the same problem and haven't been able to find a solution.  I tried to change the frequency in order to see if the filtering was a problem, but didn't see better results at other frequencies.  Could you let me know how you fixed the problem?

Thanks,

Rocco